1. Field of the Invention
The present invention relates to a multilayer interconnection board and a method of producing the multilayer interconnection board, and particularly, to a multilayer interconnection board and a production method thereof, in which a first interconnection and a second interconnection having a width and an area greater than a width and an area of the first interconnection are formed in the same layer, a via hole is formed in a resin member on the second interconnection by imprinting press, and a via is provided in the via hole.
2. Description of the Related Art
Along with requirements of enhanced performance and decreased size of recent electronic communication apparatuses, development has been made in the field of print-circuit boards, specifically a multilayer interconnection board on which plural layers of interconnection circuits are formed to increase density of the circuits. For example, there is a kind of multilayer interconnection board produced by a so-called “build-up method”, in which interconnection layers and insulating layers are stacked alternately, and vias are provided between an upper interconnection layer and a lower interconnection layer for connecting the two interconnection layers. Here, a “via” is a hole opened in an insulating layer and filled with metal for connection between conductive materials separated by the insulating layer.
In the build-up method, usually, first, a via hole is formed by a laser; next, an electric plating seed layer is formed by electric plating; and then, a plating resist is formed. After that, the via hole and an interconnection portion are filled with metal by electric plating. Finally, the seed layer on areas other than the plating resist and the interconnection portion is removed, thereby, obtaining the interconnection. This process is called as a “semi-additive process”.
The interconnections to be connected by vias have widths distributed in a range from a few tens of microns to a few mm. Further, positions of vias relative to the interconnections are determined by layouts of layers in which the vias are formed. Hence, vias are formed at various positions relative to the interconnections as required.
In the above process, when opening a hole with a laser beam, a difference of material properties between the insulating layer and the metal of the conductive layer is utilized, and by using a laser beam having strength allowing the insulating layer only to be removed, the via hole is formed without removing the conductive metal.
However, in the build-up method of the related art, because it is necessary to form via holes separately, and after that, interconnection patterns are formed separately, the number of steps increases along with an increasing number of the layers, and this increases cost of fabrication.
To solve this problem, recently, a method has been proposed in which a tool having projecting portions formed thereon for forming interconnection grooves and via holes is pressed against the insulating layer, that is, carrying out pressing working, so as to form the interconnection grooves and the via holes at one time. For example, Japanese Laid Open Patent Application No. 2002-171048 discloses such a technique. By imprinting press, the fabrication process can be simplified and the fabrication cost can be reduced.
Descriptions are made of a process of forming a multilayer interconnection board by imprinting press in the related art with reference to FIG. 1 through FIG. 6.
FIG. 1 is a cross-sectional view showing a step of forming interconnection grooves and via holes in a resin in the process of forming a multilayer interconnection board in the related art.
As illustrated in FIG. 1, plural first interconnection grooves 13 having widths of several microns and plural second interconnection grooves 14 (only one is illustrated in FIG. 1) having greater widths (for example, several mm) and greater areas than the first interconnection grooves 13 are formed in a resin 12, and the first interconnection grooves 13 and the second interconnection grooves 14 are formed in the same layer irregularly.
Here, a width of an interconnection groove is defined to be a size of the interconnection groove along a direction perpendicular to the longitudinal direction of the interconnection groove.
FIG. 2 is a cross-sectional view showing a step of plating a whole surface of an insulating film in the process of forming a multilayer interconnection board in the related art.
As illustrated in FIG. 2, in order to bury metal into the interconnection grooves and via holes formed in FIG. 1, plating is executed on the whole surface of an insulating film.
When burying a plating film 17 into the first interconnection grooves 13, the second interconnection grooves 14, and via holes 15, since the first interconnection grooves 13 and the via holes 15 are fine patterns, appropriate plating conditions are required in order to obtain good burying properties of the first interconnection grooves 13 and the via holes 15. When such plating conditions are used, however, because the second interconnection grooves 14 have greater widths and greater areas than the first interconnection grooves 13, the second interconnection grooves 14 degrade cannot be buried sufficiently, as illustrated in FIG. 2.
FIG. 3 is a cross-sectional view showing a step of partially removing metal from the surface of the insulating film in the process of forming a multilayer interconnection board in the related art.
As illustrated in FIG. 3, the metal layer formed in FIG. 2 is partially removed by polishing from areas other than those used as interconnections and vias until the surface of the insulating film is exposed, thereby, forming interconnections in the resin 12.
As described above, when an interconnection groove has a large width, and the metal buried by plating in the interconnection groove is not sufficient, as illustrated in FIG. 3, while first interconnections 19 formed in the first interconnection grooves 13 are in good shape, second interconnections 22 formed in the second interconnection grooves 14 have insufficient heights, and in a region A, a plating film 17 does not exist from the upper surfaces 22A of the second interconnections 22 to the upper surface 12A of the resin 12.
FIG. 4 is a cross-sectional view showing a step of imprinting press on the structure in FIG. 3 in the process of forming a multilayer interconnection board in the related art.
As illustrated in FIG. 4, a resin 24 is provided on the structure in FIG. 3, and a tool is pressed against the resin 24 to form interconnection grooves 28 and via holes 26. Because the portion of the bottom surface 26A of the tool corresponding to one of the via holes 26 is set to be in contact with the upper surface 12A of the resin member 12, and because the plating film 17 does not exist in the second interconnection 22 from the upper surfaces 22A of the second interconnection 22 to the upper surface 12A of the resin 12, the via hole 26 cannot reach the second interconnections 22, and the resin 24 buries the region A in the second interconnection 22. Hence, there arises a problem in that vias and the second interconnections 22 are not electrically connected even when the via hole 26 is filled with metal.